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Memory Alpha
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61	1 NAND Flash Architectures Reducing Write Amplification Through Multi-Write Codes Saher Odeh and Yuval Cassuto Technion EE Department Add to Reading List Source URL: storageconference.us Language: English - Date: 2014-06-07 16:50:12 Non-volatile memory Write amplification Flash memory Solid-state drive CPU cache DEC Alpha Computer data storage Computer hardware Computer memory Computing
62	THE RICHARD H. AULEBACH SCHOLARSHIP This scholarship was established in 2004, in memory of Richard H. Aulebach, CLAS[removed]Rick was a true Wahoo. At the University he was a member of the Pi Kappa Alpha fraternity and Add to Reading List Source URL: uvamain.uvaalumniassocia.netdna-cdn.com Language: English - Date: 2014-09-22 15:28:18 Email Academia Association of American Universities Association of Public and Land-Grant Universities University of Virginia
63	IN MEMORY AND HONOR OF MARY REINER MOTHER, WIFE, COLLEAGUE, FRIEND, NATIVE HEALTH RESEARCHER Mary Reiner passed away January 15, 2014, after a long illness related to liver disease caused by Alpha 1 antitrypsin deficienc Add to Reading List Source URL: nativeresearchnetwork.org Language: English - Date: 2014-02-04 20:24:43 Health promotion Inequality Medical sociology Public health Native Americans in the United States Indian Health Service Health Medicine Health equity
64	http://[removed]index.php?title=Getting_started&printable=y Add to Reading List Source URL: wiki.unify.com Language: English - Date: 2013-10-14 10:17:33 Hypertext Social information processing Software Computing Online encyclopedias Wiki English Wikipedia Wiki journalism Memory Alpha World Wide Web Wikis Human–computer interaction
65	1 A Pipelined Asynchronous Cache System Mika Nystr¨om, Andrew M. Lines, Alain J. Martin Abstract— We present the design of a pipelined cache system for use Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2008-06-02 20:27:46 Central processing unit Computing CPU cache Microarchitecture Cache Alpha 21064 Dynamic random-access memory MIPS architecture Translation lookaside buffer Computer hardware Computer architecture Computer memory
66	Design and Evaluation of the Hamal Parallel Computer J.P. Grossman Project Aries Add to Reading List Source URL: www.ai.mit.edu Language: English - Date: 2002-12-03 13:16:17 Data types Computer hardware Central processing unit Computer architecture CPU cache Alpha Arietis Pointer Address space Page table Computing Computer memory Virtual memory
67	IN MEMORY AND HONOR OF MARY REINER MOTHER, WIFE, COLLEAGUE, FRIEND, NATIVE HEALTH RESEARCHER Mary Reiner passed away January 15, 2014, after a long illness related to liver disease caused by Alpha 1 antitrypsin deficienc Add to Reading List Source URL: www.nativeresearchnetwork.org Language: English - Date: 2014-02-04 20:24:43 Health promotion Inequality Medical sociology Public health Native Americans in the United States Indian Health Service Health Medicine Health equity
68	3UHVHQWHGDWWKH+3&$:RUNVKRSRQ&RPSXWHU$UFKLWHFWXUH (YDOXDWLRQ8VLQJ&RPPHUFLDO:RUNORDGV System Design Considerations for a Commercial Application Environment Luiz André Barroso and Kourosh Gharachorloo Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:35:25 Computing DEC Alpha Cache Computer memory Parallel computing Supercomputers Computer architecture Computer hardware Central processing unit
69	A Detailed Comparison of Two Transaction Processing Workloads Robert Stets, Kourosh Gharachorloo, and Luiz André Barroso (1) Western Research Laboratory Hewlett-Packard Company 1501 Page Mill Road Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:38:04 Computer memory Central processing unit Cross-platform software Relational database management systems Transaction Processing Performance Council CPU cache Benchmark Transaction processing DEC Alpha Computer hardware Computer architecture Computing
70	To appear in Proceedings of the 28th Annual International Symposium on Computer Architecture, June 2001, Sweden. Code Layout Optimizations for Transaction Processing Workloads Alex Ramirez, Luiz Andr´e Barrosoy, Kouro Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:35:58 Computer architecture Cache CPU cache Computer memory Compiler optimization Inline expansion Program optimization Alpha 21164 Microarchitecture Computer hardware Computing Central processing unit

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